A complementary metal-oxide-silicon (CMOS) image sensor is a device for converting optical images into electrical signals. The CMOS image sensor uses MOS transistors as switching devices for sequentially transferring electrical signals. A CMOS image sensor has certain advantages over a charge coupled device (CCD) image sensor. For example, the CMOS image sensor costs less to manufacture and consumes less power than a CCD image sensor. In addition, a CCD image sensor is more difficult to fabricate than the CMOS image sensor. Random access is impossible in the CCD image sensor, but is possible in the CMOS image sensor. From the late 1990's to recently, CMOS fabricating techniques have been developed and signal processing algorithms have been enhanced to improve the CMOS image sensor.
According to the number of transistors included in a unit pixel, the CMOS image sensor is categorized as 1-transistor structure, 2-transistor structure, 3-transistor structure, and 4-transistor structure. The 1-transistor structure has a high fill-factor (i.e., percentage of light sensitive area of a pixel) but suffers from loud noise. Accordingly, some CMOS image sensors adopt the 3-transistor structure and the 4-transistor structure. As compared to the 4-transistor structure, the 3-transitor structure has a lower manufacturing cost, higher fill-factor, and excellent properties for image lagging and blooming.
A method of fabricating a conventional CMOS image sensor having a 3-transistor structure is explained with reference to FIG. 1.
Referring to FIG. 1, a device isolation layer 20 is formed at a predetermined region of a semiconductor substrate 10 to define an active region. A silicon oxide layer is formed on the active region to be a gate insulating layer 30. A gate conductive layer is formed on the semiconductor substrate 10 including the gate insulating layer 30. The gate conductive layer is patterned to form a plurality of gate conductive patterns 40 across the active region. The gate conductive patterns 40 constitute gate electrodes of a reset transistor, a selection transistor, and an access transistor, which, in turn, constitute a CMOS image sensor having the 3-transistor structure. Only the gate conductive pattern 40 constituting the gate electrode of the reset transistor is illustrated in FIG. 1.
Following formation of the gate conductive pattern 40, a lightly doped region 94 is formed at the active region around the gate conductive pattern 40. A photodiode region 99 is formed at the active region adjacent to a source region of the reset transistor. Light impinges on the photodiode region 99. Following formation of the lightly doped region 94 and the photodiode region 99, a spacer 50 is formed on sidewalls of the gate conductive pattern 40. Using the spacer 50 as a mask, an ion implanting process is carried out to form a heavily doped region 92 which may constitute source and/or drain regions of the reset, select, and access transistors. During formation of the heavily doped region 92, a floating diffusion region 96 is formed and connected to the source of the reset transistor.
An interlayer dielectric layer 60 is formed on the semiconductor substrate including the heavily doped region 92. The interlayer dielectric layer 60 is patterned to form an opening 65 exposing a top surface of the floating diffusion region 96, the heavily doped region 92, and the gate conductive pattern 40. By a method known to those of skill in the art, a plug/interconnection 70 is formed to interconnect the source and/or drain and the gate of the transistors.
In a case where the floating diffusion region 96 is formed by the ion implanting process, the kinetic energy of the ions causes lattice defects, e.g., dislocation and vacancies, in the floating diffusion region 96. Since a patterning process for forming the opening 65 includes a step of anisotropically etching the interlayer dielectric layer 60 using plasma, the floating diffusion region 96 is damaged. Additionally, a conventional siliciding process for reducing a resistance is carried out to contaminate the floating diffusion region 96 with metal materials. The floating diffusion region 96, which is a component of a CMOS image sensor, has a significant influence on the characteristics of the CMOS image sensor. In order to achieve desirable characteristics of the CMOS image sensor, lattice defects, etching damage, and metal contamination in the floating diffusion region must be minimized. Accordingly, there exists a need for a CMOS image sensor that minimizes such defects and a method of fabricating same.